Please use this identifier to cite or link to this item: http://hdl.handle.net/10662/24075
Title: Fast Montgomery Modular Multiplier using FPGAs
Authors: Pajuelo Holguera, Francisco
Granado Criado, José María
Gómez Pulido, Juan Antonio
Keywords: Criptografía;Cryptography;FPGA;FPGA;Síntesis de alto nivel;High-level synthesis;Mutiplicación modular Montgomery;Montgomery modular multiplication;Paralelismo;Parallelism
Issue Date: 2022
Publisher: IEEE
Abstract: This letter details a fast and efficient implementation of the Montgomery modular multiplication by taking advantage of parallel multipliers and adders. This implementation was programmed in high-level synthesis language and tested on a field-programmable gate array device. In order to test the performance of the proposal, a sequential version of the algorithm was also implemented in hardware. Moreover, we compared the parallel implementation with a software version and with five contributions from the literature. This way, we found that our proposal improves the performance of all other implementations.
URI: http://hdl.handle.net/10662/24075
ISSN: 1943-0663
DOI: 10.1109/LES.2021.3090029
Appears in Collections:DTCYC - Artículos

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